Like previous generations of QuiXilica products based on Virtex II Pro and Virtex 5 technology, the Aries-V6 is compatible with legacy VME systems as well as newer ANSI/VITA 41 VXS based systems in both laboratory and deployed / rugged applications.

The Aries-V6 has ten Analogue Devices AD9467 ADC converters, providing 16-bit resolution at sample rates up to 250 MSPS with an input bandwidth of 500 MHz. The ADC provides an Effective Number of Bits (ENOB) of 12.1 along with typical SFDR of 95 dBc and SNR of 74 dBFS when using a 97 MHz input. Each 6U card has a single clock and trigger input which is used for all input channels. The trigger signal may be used to support coherent processing across multiple Aries-V6 boards in a system, with up to 180 channels in a single chassis.

The Aries-V6 has three, highly connected, Xilinx Virtex-6 FPGA sites as shown in the attached block diagram. The two front-end FPGAs are attached directly to the A/D converters, providing a simple and direct high speed connection for signal processing of the input data streams. The third FPGA can be used to support additional processing, and also any required protocol support for either front panel or backplane interfaces.

The Aries-V6 provides a rich set of network interconnect options for both control and data plane communications. An onboard Gigabit Ethernet switch provides an integrated LAN-on-board network which connects the front panel interface, backplane interfaces, FPGA nodes, and system management processor into a local area network for control and status monitoring. The VXS backplane fabric interface can also support dual 10 Gigabit Ethernet interconnect using 10GBASE-KX4 interfaces with appropriate protocol cores in the back end FPGA.