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Additional Information - Avionics Databus Test, Analysis & Simulation |
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With several new aircraft now under development that utilise a
number of different data buses and data networks in the same system,
the task of avionics integration and testing has grown to become
more complex and challenging. A typical example is that of the Airbus
Industries A400M Military Transport Aircraft. The A400M will use
a combination of data buses and networks including MIL-STD-1553B,
ARINC429 and Avionics Full Duplex Switched Ethernet (AFDX). In this
heterogeneous data bus environment special types of test and analysis
tools are required in order to fully rationalise and simulate the
bus either as individual entities or as intergrated systems. |
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For more information please contact UNITRONIX |
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" Programmable Timing & Sequencing of Frames " Physical Error Injection - CRC, Gap, Size, Alignment " Logical Error Injection on Layers 2, 3, 4 " Timing Error Injection - Violation of Bandwidth Allocation Gap (BAG) " Autonomous Dynamic Data Generation " UDP Port Simulation with Traffic Shaping & Sequence Numbering " Onboard support for sampling and queuing ports |
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The AMC-FDX-2 module ports can be configured to work in UDP / VL
oriented receive mode. In this mode each UDP port has a separate
buffer queue. Received frames are stored with frame headers containing
time tag and status information. Frame header information can be
stored and payload data optionally discarded for the testing of
switches and the complete network. With the Traffic shaping verification
enabled, any violations are reported as errors in related frame
headers.
" VL oriented Filtering " Second Level Filtering on Generic Frame Parameter " Time Stamping of Received Packets with extended IRIG-B time code (1µs) " Physical Error detection, Frame Level - CRC, Gap, Size and Alignment AFDX Specific Error Detection , Traffic Shaping Verification , Verification of MAC, IP and UDP Headers VL oriented Integrity Checking " Chronological Receive Mode (Monitor Mode) The AMC-FDX-2
module ports can be configured in Chronological Receive Mode to
sequentially receive frames and store them in a circular buffer.
The payload data can be discarded to optimise the use of the buffer
for frame capture and analysis. Powerful Filtering, Triggering,
Complex Triggering and Capture Modes allows users to select only
the frames, data and errors of interest. Monitor Mode also provides
activity monitoring and statistics for each VL recorded by the AMC-FDX-2
module. The interface modules report the number of frames received
and the number of errors detected globally and in VL orientated
format. |
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AIMs ARINC429, ARINC 429, ARINC-429 |
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" Cyclic/Acyclic Label Transmission Mode & support for
File Transfer Protocols " Error Injection for each Label Transfer: Short Gap, Parity, Bit Count, Coding " Programmable Gap between Labels : 0 to 255 Bits " Transmit Operation Controlled by Instruction Lists " Comprehensive Instruction Set: JUMP, CALL, COND-JUMP, TRANSFER |
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The AMC429 provides real time simulation of up to 16 ARINC429 Receiver Channels concurrently controlled by an onboard RISC Processor. " Triggering and Filtering " Upper & Lower Limit Check " Trigger on Specific or on any Error " Label Content & Sequential Dependant Trigger " Label selective & Label Data Contents Dependent Interrupt " Label selective & Label Data Contents Defendant Filter " Multi-Buffering with Real Time Data Buffer Updates For monitoring and control of an external application 16 off Discrete Input / Output ports with a wide range voltage characteristic are provided for customised use. The 8 Inputs/ 8 Outputs discrete signal ports are software controllable by the application program. " 8 discrete Inputs in the range of 3.3 ... 30 VDC " 8 discrete open collector Outputs up to 30 VDC " Fused 5 VDC provided for open collector supply An onboard 'IRIG-B' time code decoder and generator allows synchronisation of ARINC429 channels using single or multiple AMC429 modules. Multiple AMC429 modules can be synchronised to one common IRIG-B time code decoder and generator allowing synchronised time tagging of multiple ARINC429 channels. AMC429 cards can be synchronised to one common external IRIG-B time source or to the free wheeling onboard Time Code Generator of one AMC429 module. The AMC429
module is able to electrically reconstruct previously recorded ARINC429
data traffic physically to the bus with excellent timing accuracy.
Recorded data files can be selected for physical bus replay to perform
systems integration and test with the ability to disable any or
all ARINC429 labels from the recorded file. Application Support
Processor A 400 MHz Application Support Processor ASP provides unique
onboard processing functions typically provided by host processing
systems. |
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AIMs MIL-STD-1553 A/B, MIL-STD-1553, MIL STD 1553, MILSTD1553 |
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" Autonomous Operation including sequencing of Minor / Major
Frames. " Support for acyclic message insertion / deletion. " Programmable BC Retry without host interaction. " Full Error Injection down to word and bit level (AS4112 Compliant). " Multi-Buffering with Real Time Data Buffer Updates. " Synchronisation of BC operation to external trigger inputs. " 4 µsec Intermessage Gaps. |
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The AMC1553-1/2 simulates up to 31 Remote Terminals including all
sub-addresses on one or two MIL-STD-1553A/B buses concurrently with
BC and Chronological Monitor operation. Alternatively each of the
31 RT's can operate in a message oriented "Mailbox Monitor
Mode" to monitor non-simulated RT's. " Programmable RT Response Time down to 4 µsec for each simulated RT. " Programmable & Intelligent Response to Mode Codes. " Full Error Injection down to word and bit level (AS4112 Compliant). " Multi-Buffering with Real Time Data Buffer Updates. The AMC1553-1/2 offers full bus monitoring and analysis with time tagging of all bus traffic to 1µsec resolution including response time and gap time measurements down to 250nsec concurrently with BC and Multiple RT operation. Key features of the Chronological Monitor: " 100% Data Capture on two streams at full bus rates. " Autonomous message synchronisation and Full Error Detection. " Two Static/ Dynamic Complex Triggers with sequencing. " Message Filter and Selective Capture. " Bus Activity recording independent from trigger and capture mode. " External Trigger Outputs. " Programmable Response Time Out. The AMC1553-1/2 module provides Transformer Coupling and Direct Coupling with fixed output transceivers for connection to the MIL-STD-1553A/B bus via the PMC standard connector. Both coupling modes to the MIL-STD-1553A/B bus system are alternately available at the output connector or at the backpanel connector. The AMC1553-1/2 is able to electrically reconstruct previously recorded MIL-STD-1553A/B databus traffic physically to the bus with excellent timing accuracy. Recorded data files can be selected for a physical bus replay to perform systems integration and test with the ability to disable any or all RT responses from the recorded files. An on board IRIG-B time code decoder and generator allows synchronization of MIL-STD-1553A/B bus traffic using single or multiple AMC1553-1/2 modules. AMC1553 cards can be synchronised to one common IRIG-B time source from external or to the free wheeling onboard Time Code Generator of one ACM1553 module as the reference for accurate correlation of data across multiple MIL-STD-1553A/B data streams. The AMC1553-1/2 is supplied with a BSP (Board Support Package) for Windows 98/ ME/NT/2000 and embedded VME systems (e.g.VxWorks) comprising system drivers, application interface libraries, sample code and manuals. The VME BSP is provided in source code for integration support to the most usual Operating Systems. For more information please contact UNITRONIX |
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AIMs JSF Fiber Channel Single and Dual Stream test and simulation module The APG-FC2 is a high performance, intelligent Fibre Channel interface module offering full function test, data generation, simulation, monitoring and analyzer functions. It handles Point-to-point, Switched Fabric and Arbitrated Loop topologies. It's unique onboard processing capability, scalable memory resources, IRIG-B time code decoder/ generator and high-speed protocol deciphering provide users with an unparalleled capability for the most demanding avionics applications. It supports multiple protocols including JSF Anonymous Subscriber Messaging (ASM). Two variations are sold for cost efficiency, providing either Simulator or Analyzer function, under user control, or simultaneous operation as our trademarked simuliser The simuliser also adds the ability of real time archiving (data rate dependent on host), and playback of archived files. Both ports can operate at full line rates, selectable at 1.0625 Gb/s or 2.125 Gb/s. The APG-FC2 PCI module provides two Fibre Channel ports which can function completely independently, or be configured to work together for specific modes of operation. It has the ability to mirror Port 1 traffic out of Port 2 and/or "snoop" a port for specific message content, and trigger dynamic simulation on the same or other ports. Each port is supported by it's own processor and memory bank, eliminating host burden. Together they are interfaced to the PCI bus as a single device, requiring only one slot. The board supports Bus Mastering PCI with DMA. The high speed FPGA (Xilinx Virtex II) based design is, capable of the speeds and processing necessary to handle custom simulation with data dependencies, and archiving / playback with accurate timing and error reproduction. |
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The APG-FC2 provides data generation at full line rates on any level
(FC-1, FC-2 or FC-4). The user may program frame / sequence gaps and
use data generator functions for random, incrementing, decrementing
or custom defined data. It includes the ability of onboard processors
(dual Power PCs (PPC), one per port) which can execute user defined
programs in C/C++. This allows data dependent simulation, including
error injection, triggered by specific data in either the headers
or payload. The diagram to the right illustrates both channels generating
data, and the blue arrows providing custom simulation from the onboard
PPC of Port A. |
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The APG-FC2 provides the ability to mirror or echo the traffic back
out of the second Port. "Snooping" the traffic for specific
messages or events can also be used to trigger modified and/or injected
traffic out of either Port. In addition, external input and output
trigger signals can be utilized to trigger simulation on Ports residing
on separate modules, either on the same PCIbus, or in different systems.
The APG-FC2 provides the ability to inject errors and create simultaneous "Before and After" sequential logs in the memory buffers. Port A can be receiving traffic and analyzing it, while Port B also captures it. The PPC on Port B then accesses the data in Memory and can add errors into the buffers before transmitting the traffic out. This allows the user to inject errors or other type of specific traffic. To create dual logs would require both ports, but the user could configure dual channel error injection without the "Before and After" logs, for independent operation. Error injection capabilities are absolutely necessary to reproduce true archived traffic in the APG-FC2's "Playback Mode". Dual Sequential Logs are captured to memory and may be archived to Host PC storage mediums (data rates dependent on IDE or SCSI in host). The logs include all critical information such as source and destination ID, time stamp (System or IRIG-B), protocols, errors, data value, etc., and may be accessed immediately, while still being captured through our "Quick Access Monitor" capability. Captured data is defined by predetermined filters and organized for ease of sorting by the user. Triggers allow a wrap buffer to capture data before and after defined events. Specific data parameters may be monitored as the last sample received. Current Value Tables (CVTs) are then provided for display and processing. Up to 16 different parameters may be defined by the user for capture into these predefined buffers. Data (headers and payload) may be accessed and become criteria for triggering and filtering by the complex firmware modules. These allows multiple layers of triggers based on errors, timing, counts, ordered sets and external events. A trigger sequence allows And, Or and Arm functions between triggers. Output triggers are supplied to the external connector and multiple modules may share these triggers between ports. Data can then be filtered based on similar criteria and captured, archived or dropped. An onboard IRIG-B decoder and generator provides the synchronisation between multiple boards and precision time stamping of all captured data in the sequential log, per an External IRIG-B Signal, the host system clock, or a user provided time. This is especially useful when working with on the data buses at the same time IE: 1553 and JSF fiber channel. For more information please contact UNITRONIX |
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UNITRONIX |
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